Ro_Patel
$CDNS expands partnership w/ $TSM to deliver advanced capabilities for AI & HPC designers
Cadence has achieved tool certification for TSMC’s advanced A14 process, demonstrated an industry-leading UALink solution in TSMC N3P, & introduced new silicon-proven IP for N3P & N2P technologies
Cadence's digital full flow, signoff flow, and custom/analog flows are now certified for TSMC A16 &A14 process technologies. The digital full flow features the Innovus Implementation System, Cadence Cerebrus Intelligent Chip Explorer for DTCO, & enhanced signoff tools including the Tempus Timing & ECO Solution, EMX Planar 3D Solver, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Pegasus Verification System, the Liberate Characterization Portfolio, & the enabled Genus Synthesis Solution
This partnership, the companies are enabling agentic AI chip & 3D-IC design flows across TSMC's N3, N2, A16 & A14 process technologies, including TSMC 3DFabric support for wafer-scale systems with hundreds of chiplets
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