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Intel (INTC) and ASML (ASML) announced Monday that they have deepened their multiyear collaboration on High NA EUV lithography. Rivals Samsung and TSMC (TSM) are also lining up to adopt the technology, though on longer adoption timelines.
High NA EUV is a next-generation machine technology from ASML that helps chipmakers print smaller and more complicated features onto semiconductor wafers.
Intel is already using the technology in high-volume production, while Samsung plans to bring it into DRAM manufacturing by 2028 and TSMC plans to use it for advanced chips from 2030.
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INTC stock jumped over 4% in pre-market trade and was among the top trending tickers on the platform. ASML stock rose nearly 3%, and TSM stock moved 1.5% higher amid weakness in the broader market. On Stocktwits, retail sentiment around INTC and TSM remained in ‘neutral’ territory over the past day, while sentiment around ASML trended in the ‘bullish’ zone.

Intel Foundry and ASML said more than one million wafers have now been processed using High NA EUV equipment. That includes testing and development work, along with actual production of some layers of Intel's Core Ultra Series 3 processors, code-named Panther Lake.
Intel said the machines are performing as expected in areas including accuracy, production speed and availability. It also said chips made using High NA EUV on its 18A manufacturing process are matching or exceeding the performance of comparable layers made using ASML's existing EUV technology.
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ASML CEO Christophe Fouquet called Intel "one of the key leaders of the industry's adoption of High NA," and pointed to its role in bringing the technology into commercial production.
Samsung plans to use High NA EUV for high-volume DRAM production by 2028. That would bring the technology into memory chips, rather than limiting it to advanced processors.
TSMC plans to use High NA EUV for advanced-node chip production starting in 2030. The company expects to need the technology on more layers of its chips over time as chip designs become more complicated, particularly for AI applications.
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Today, chipmakers use 6-inch masks, which are essentially templates that contain the patterns to be printed onto a wafer. ASML, Intel, TSMC, Samsung and other industry participants are working toward larger 12-inch masks.
The larger masks could allow chipmakers to print bigger areas of a chip at once. That could reduce the need to piece together different exposures, improve factory productivity, and lower manufacturing costs.
ASML and TSMC are targeting a pilot line for the larger masks by 2031, with the technology expected to be ready for advanced-node production by 2033.
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In the meantime, Intel and ASML are working on "reticle stitching," which allows chipmakers to use High NA EUV with today's 6-inch masks.
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